Package for semiconductor chip having thin recess portion and thick plane portion

ABSTRACT

In a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a package for a semiconductor chip, andmore particularly, to a package having a recess portion for mounting asemiconductor chip and a plane portion for mounting a metal patternlayer.

2. Description of the Related Art

A prior art package includes a heat spreader (metal plate) having arecess portion for mounting a semiconductor chip and a plane portion formounting a metal pattern layer. The metal plate has a uniform thickness,and a recess having a predetermined depth is formed in the metal plateby a pressing process using metal molds (see Ashtok Domadia et al., TBGABond Process for Ground and Power Plane Connections”, IEEE 1996Electronic Components and Technology Conference, pp. 707-712). This willbe explained later in detail.

In the above-described prior art package, since the recess is formed inthe metal plate by a pressing process, it is impossible to remarkablyincrease the thickness of the metal plate. Even in this case, thethickness of the metal plate is increased by a moderate value toincrease the rigidity of the plane portion thereof. This is advantageousin terms of the handling of the package and forming solder balls.Simultaneously, the rigidity of the metal plate around the recess isincreased. Therefore, strain generated in the metal plate around thesemiconductor chip due to the heating thereof is hardly leaked throughthe metal plate around the recess thereof, so that large stress isapplied to the back surface of the semiconductor chip. Thus, thesemiconductor chip is easily peeled from the metal plate, whichdeteriorates the reliability of the package.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a package for asemiconductor chip capable of decreasing the manufacturing cost.

Another object is to improve the reliability of a package for asemiconductor chip.

According to the present invention, in a package for mounting includinga metal plate having a recess portion for mounting a semiconductor chipand a plane portion for mounting a metal pattern layer, the recessportion is thinner than the plane portion.

Also, in a method for manufacturing a package including a metal plateincluding a recess portion for mounting a semiconductor chip and a planeportion for mounting a metal pattern layer, a photoresist pattern layeris formed to cover the plane portion of the metal plate, and the metalplate is etched by using the photoresist pattern layer as a mask.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from thedescription set forth below, as compared with the prior art, withreference to the accompanying drawings, wherein:

FIG. 1 is a cross-sectional view illustrating a prior art package;

FIG. 2 is a cross-sectional view illustrating a first embodiment of thepackage according to the present invention;

FIG. 3 is a partial perspective view of the package of FIG. 2;

FIGS. 4A through 4H are cross-sectional views for explaining the methodfor manufacturing the package of FIGS. 2 and 3.

FIG. 5 is a cross-sectional view illustrating a second embodiment of thepackage according to the present invention; and

FIGS. 6A through 6H are cross-sectional views for explaining the methodfor manufacturing the package of FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before the description of the preferred embodiments, a prior art packagewith be explained with reference to FIG. 1 (see: Ashtok Domadia et al.,“TBGA Bond Process for Ground and Power Plane Connections”, IEEE 1996Electronic Components and Technology Conference, pp. 707-712).

In FIG. 1, which illustrates a prior art one-connection-layer type ballgrid array (BGA) type package, a heat spreader 101 made of metal has auniform thickness, and a recess 101 a having a predetermined depth isformed in the heat spreader 101 by a pressing process using metal molds.Note that the heat spreader 101 also serves as a ground plane layer.

A power supply plane layer 102 is adhered by an adhesive layer 103 on aplane portion 101 b of the heat spreader 101. Also, an organicinsulating pattern layer 104 is adhered by an adhesive layer 105 on thepower supply plane layer 102.

On the other hand, a semiconductor chip 106 is mounted in the recess 101a of the heat spreader 101 by a mount material layer 107 made of Agpaste.

Electrodes 106 a of the semiconductor chip 106, the heat spreader 101,the power supply plane layer 102 and the like are electrically connectedby copper foil connection lines 108 using a tape automated bonding (TAB)process.

The semiconductor chip 106 is sealed by a thermosetting resin layer 109.

Solder balls 110 as external electrodes are formed on the copper foilconnection lines 108.

In the package of FIG. 1, since the recess 101 a is formed in the heatspreader 101 by a pressing process, it is impossible to remarkablyincrease the thickness of the heat spreader 101. Even in this case, thethickness of the heat spreader 101 is increased by a moderate value toincrease the rigidity of the plane portion 101 b of the heat spreader101. This is advantageous in terms of the handling of the package andforming the solder balls 110. Simultaneously, the rigidity of the heatspreader 101 around the recess 101 a thereof as indicated by X in FIG. 1is increased. Therefore, strain generated in the heat spreader 101around the semiconductor chip 106 due to the heating thereof is hardlyleaked through the heat spreader 101 around the recess 101 a thereof, sothat large stress is applied to the back surface of the semiconductorchip 106 and the mount material layer 107. Thus, the semiconductor chip106 is easily peeled from the heat spreader 101, which deteriorates thereliability of the package.

Note that, if the heat spreader 101 is constructed in advance so thatthe center portion is thin to decrease the rigidity thereof and theperipheral portion is thick, to increase the rigidity thereof, theabove-mentioned disadvantages are dissolved. However, in this case, themanufacturing steps become complex, which increases the manufacturingcost.

In FIG. 2, which illustrates a first embodiment of the package accordingto the present invention, a heat spreader 1 made of copper or aluminumhas a thin recess portion 1 a and a thick plane portion 1 b. Note thatthe heat spreader 1 also serves as a ground plane layer.

An organic insulating pattern layer 2 made of polyimide is formed on theplane portion 1 b of the heat spreader 1, and a metal pattern layer 3made of copper foil is formed on the organic insulating pattern layer 2.

On the other hand, a semiconductor chip 4 is mounted on the recessportion 1 a of the heat spreader 1 by a mount material layer 6 made ofAg paste.

Electrodes 4 a of the semiconductor chip 4, the heat spreader 1 and themetal pattern layer 3 are electrically connected by bonding wire 6 madeof Au.

The semiconductor chip 4 is sealed by a thermosetting resin layer 7. Inthis case, a dam 8 is provided to prevent the thermosetting resin layer7 from being leaked into the plane portion 1 b of the heat spreader 1.

Solder balls 9 as external electrodes are formed on the metal patternlayer 3. In this case, each of the solder balls 9 is connected via themetal pattern layer 3 at throughholes 2 a of the organic insulatingpattern layer 2 to land patterns 10. Note that the land patterns 10 areformed by etching the heat spreader 1.

In FIG. 3, which is a partial perspective view of the package of FIG. 2,the recess portion 1 a of the heat spreader 1 has a thickness T_(a) andthe plane portion 1 b of the heat spreader 1 has a thickness T_(b)(>T_(a)). For example,

T_(b)=0.20˜0.50 mm (preferably, about 0.20mm)

T_(a)=T_(b)−about 20 to 50 μm

Also, the organic insulating pattern layer 2 has a thickness of T₂ ofabout 25 to 60 μm, preferably about 50 μm.

Further, the metal pattern layer 3 has a thickness T₃of about 18 to 35μm, preferably about 20 μm.

In the package of FIGS. 2 and 3, since the recess portion 1 a is formedin the heat spreader 1 by an etching process as will be explained later,it is possible to remarkably increase the thickness of the heat spreader1. As a result, the rigidity of the plane portion 1 b of the heatspreader 1 can be sufficiently increased. This is advantageous in termsof the handling of the package and forming the solder balls 9.Simultaneously, the rigidity of the heat spreader 1 around the recessportion 1 a thereof as indicated by Y in FIGS. 2 and 3 can be decreased.Therefore, strain generated in the heat spreader 1 around thesemiconductor chip 4 due to the heating thereof is easily leaked throughthe heat spreader 1 around the recess portion 1 a thereof, so that largestress is hardly applied to the back surface of the semiconductor chip 4and the mount material layer 5. Thus, the semiconductor chip 4 is hardlypeeled from the heat spreader 1, which improves the reliability of thepackage.

The method for manufacturing the package of FIGS. 2 and 3 will beexplained with reference to FIGS. 4A through 4H.

First, referring to FIG. 4A, an about 50 μm thick organic insulatinglayer 20 made of polyimide is coated on an about 0.2 mm thick metalplate (heat spreader) 1 of copper or aluminum. Then, a metal layer 30-amade of copper is deposited on the organic insulating layer 20. Then, aphotoresist pattern layer 401 is formed by a photolithography process.

Next, referring to FIG. 4B, the metal layer 30-a is etched by using thephotoresist pattern layer 401 as a mask, to form a metal pattern layer3-a. In this case, a through hole 2 a having a diameter of about 0.1 mmis perforated in the metal pattern layer 3-a. Then, the photoresistpattern layer 401 is removed.

Next, referring to FIG. 4C, the organic insulating layer 20 is etched byusing the metal pattern layer 3-a as a mask, to form an organicinsulating pattern layer 2. Note that the through hole 2 a is furtherdeepened.

Next, referring to FIG. 4D, an about 25 μm thick metal layer 30-b madeof copper is plated on the entire-surface.

Next, referring to FIG. 4E, a photoresist pattern layer 402 for coveringa plane portion of the metal plate 1 is formed by a photolithographyprocess.

Next, referring to FIG. 4F, the metal layer 30-b is etched by using thephotoresist pattern layer 402 as a mask, to form a metal pattern layer3-b. The metal pattern layers 3-a and 3-b form a metal pattern layer 3.In this case, the metal plate 1 is also etched, so that the metal plate1 is divided into a thin portion, i.e., a recess portion 1 a and a thickportion, i.e., a plane portion 1 b. Then, the photoresist pattern layer402 is removed.

Next, referring to FIG. 4G, the plane portion 1 b of the metal plate 1is etched to form a landpattern 10.

Next, referring to FIG. 4H, a pressing process using metal molds isperformed upon the recess portion 1 a of the metal plate 1, to form arecess therein.

Finally, a semiconductor chip (not shown) is mounted on the recessportion 1 a of the heat spreader 1 by a mount material layer (not shown)made of Ag paste. Then, electrodes of the semiconductor chip, the metalplate 1 and the metal pattern layer 3 are electrically connected bybonding wire (not shown) made of Au. Then the semiconductor chip issealed by a thermosetting resin layer (not shown). Also, solder balls(not shown) as external electrodes are formed on the metal pattern layer3. In this case, each of the solder balls 9 is connected via the metalpattern layer 3 at through holes 2 a of the organic insulating patternlayer 2 to the land patterns 10. Thus, the package of FIGS. 2 and 3 iscompleted.

In the method as illustrated in FIGS. 4A through 4H, since the processof etching the metal plate 1 for the recess portion 1 a thereof iscarried out simultaneously with the process of etching the metal layer30-b for the metal pattern layer 3, the manufacturing steps can besimplified, which decreases the manufacturing cost. In addition, sincethe TAB process and the process using the adhesive layers 103 and 105 asin the prior art package of FIG. 1 are unnecessary, the manufacturingsteps can be further simplified, which also decreases the manufacturingcost.

In FIG. 5, which illustrates a second embodiment of the packageaccording to the present invention, a plurality of pedestal typeprotrusions 11 having a height of about 5 to 10 μm are provided on therecess portion 1 a of the metal plate 1. As a result, the contactsurface of the mount material layer 5 in contact with the metal plate 1is increased, so that the tight contact characteristics of thesemiconductor chip 1 to the metal plate 1 are improved, which improvesthe reliability of the package.

The method for manufacturing the package of FIG. 5 will be explainednext with reference to FIGS. 6A through 6H.

First, referring to FIG. 6A, in the same way as in FIG. 4A, an about 50μm thick organic insulating layer 20 made of polyimide is coated on anabout 0.2 mm thick metal plate (heat spreader) 1 of copper or aluminum.Then, a metal layer 30-a made of copper is deposited on the organicinsulating layer 20. Then, a photoresist pattern layer 401 is formed bya photolithography process.

Next, referring to FIG. 6B, in the same way as in FIG. 4B, the metallayer 30-a is etched by using the photoresist pattern layer 401 as amask, to form a metal pattern layer 3-a. In this case, a throughhole 2 ahaving a diameter of about 0.1 mm is perforated in the metal patternlayer 3-a. Then, the photoresist pattern layer 401 is removed.

Next, referring to FIG. 6C, in the same way as in FIG. 4C, the organicinsulated layer 20 is etched by using the metal pattern layer 3-a as amask, to form an organic insulating pattern layer 2. Note that thethroughhole 2 a is further deepened.

Next, referring to FIG. 6D, in the same way as in FIG. 4D, an about 25μm thick metal layer 30-b made of copper is plated on the entiresurface.

Next, referring to FIG. 6E, in a similar way to FIG. 4E, a photoresistpattern layer 402′ for covering a plane portion of the metal plate 1 isformed by a photolithography process. In this case, the photoresistpattern layer 402′ has a grid shape pattern including rectangles ofabout 50 to 100 μm in a recess portion of the metal plate 1.

Next, referring to FIG. 6F, in the same way as in FIG. 4F, the metallayer 30-b is etched by using the photoresist pattern layer 402 as amask, to form a metal pattern layer 3-b. The metal pattern layers 3-aand 3-b form a metal pattern layer 3. In this case, the metal plate 1 isalso etched, so that the metal plate 1 is divided into a thin portion,i.e., a recess portion la and a thick portion, i.e., a plane portion 1b. Also, a plurality of pedestal type protrusions 11 having a height ofabout 5 to 10 μm are formed in the recess portion 1 a. Then, thephotoresist pattern layer 402′ is removed.

Next, referring to FIG. 6G, in the same way as in FIG. 4G, the planeportion 1 b of the metal plate 1 is etched to form a landpattern 10.

Next, referring to FIG. 6H, in the same way in FIG. 4H, a pressingprocess using metal molds is performed upon the recess portion 1 a ofthe metal plate 1, to form a recess therein. In this case, one of themetal molds abutting the protrusions 11 is adjusted so that theclearance theretween is about several μm.

Finally, in the same way as in the method for the first embodiment, asemiconductor chip (not shown) is mounted on the recess portion 1 a ofthe heat spreader 1 by a mount material layer (not shown) made of Agpaste. Then, electrodes of the semiconductor chip, the metal plate 1 andthe metal pattern layer 3 are electrically connected by bonding wire(not shown) made of Au. Then the semiconductor chip is sealed by athermosetting resin layer (not shown). Also, solder balls (not shown) asexternal electrodes are formed on the metal pattern layer 3. In thiscase, each of the solder balls 9 is connected via the metal patternlayer 3 at throughholes 2 a of the organic insulating pattern layer 2 tothe land patterns 10. Thus, the package of FIG. 5 is completed.

Note that when the package of FIGS. 2 and 5 is mounted on a printedcircuit board, the package is faced down, so that the solder balls 9 arein contact with the printed circuit board. Also, the land patterns 10are used for testing the electrical contact of solder balls 9 to themetal pattern layer 3.

Although the above-described embodiments relate to a BGA type package,the present invention can be applied to other types of packages.

As explained hereinabove, according to the present invention, themanufacturing steps can be simplified to decrease the manufacturingcost. In addition, the reliability can be improved.

What is claimed is:
 1. A method for manufacturing a package including ametal plate including a recess portion for mounting a semiconductor chipand a plane portion for mounting a metal pattern layer, comprising thesteps of: forming a photoresist pattern layer for covering said planeportion of said metal plate including said recess portion for mountingsaid semiconductor chip and said plane portion for mounting said patternlayer; and etching said metal plate by using said photoresist patternlayer as a mask.
 2. A method for manufacturing a package including ametal plate including a recess portion for mounting a semiconductor chipand a plane portion for mounting a metal pattern layer, comprising:forming a photoresist pattern layer for covering said plane portion ofsaid metal plate; and etching said metal plate by using said photoresistpattern layer as a mask, wherein said photoresist pattern layer has aplurality of patterns on said recess portion of said metal plate, sothat a plurality of protrusions are formed on said recess portion ofsaid metal plate.
 3. A method for manufacturing a package for mountingincluding a metal plate including a recess portion for mounting asemiconductor chip and a plane potion for mounting a metal patternlayer, comprising the steps of: forming an insulating layer on a metalplate; forming a first metal layer on said insulating layer; forming afirst photoresist pattern layer on said first metal layer above saidplane portion of said metal plate; etching said first metal layer byusing said first photoresist pattern layer as a mask; removing saidfirst photoresist pattern layer after said first metal layer is etched;etching said insulating layer by using said first metal layer as a maskafter said first photoresist pattern layer is removed; forming a secondmetal layer on said metal plate and said first metal layer after saidinsulating layer is etched; and forming a second photoresist patternlayer on said second metal layer above said plane portion of said metalplate; etching said second metal layer and said recess portion of saidmetal plate by using said second photoresist pattern.
 4. The method asset forth in claim 3, wherein said second photoresist pattern layer hasa plurality of patterns on said recess portion of said metal layer. 5.The method as set forth in claim 3, wherein said first photoresistpattern layer has a throughhole on said plane portion of said metalplate.
 6. The method as set forth in claim 3, wherein said second metallayer forming step forms said second metal layer by using a platingprocess.
 7. A method of manufacturing a package for a semiconductorchip, comprising: providing a metal plate comprising a recess portionfor mounting a semiconductor chip and a plane portion for mounting ametal pattern layer, wherein said recess portion is thinner than saidplane portion; forming a photoresist layer having a plurality ofpatterns on said recess portion; and etching said metal plate so that aplurality of protrusions are formed on said recess portion.
 8. Themethod of manufacturing a package as set forth in claim 7, wherein saidrecess portion has a plurality of protrusions for facing saidsemiconductor chip.
 9. A method for manufacturing a package including ametal plate including a recess portion for mounting a semiconductor chipand a plane portion for mounting a metal pattern layer, comprising:forming a photoresist pattern layer for covering said plane portion ofsaid metal plate including said recess portion for mounting saidsemiconductor chip and said plane portion for mounting said patternlayer; and etching said metal plate by using said photoresist patternlayer as a mask.
 10. A method for manufacturing a package for mountingincluding a metal plate including a recess portion for mountingsemiconductor chip and a plane portion for mounting a metal patternlayer, comprising: forming a first metal layer on an insulating layer;forming a first photoresist pattern layer on said first metal layerabove said plane portion of said metal plate; etching said first metallayer by using said first photoresist pattern layer as a mask; forming asecond metal layer on said metal plate and said first metal layer;forming a second photoresist pattern layer on said second metal layerabove said plane portion of said metal plate; and etching said secondmetal layer and said recess portion of said metal plate by using saidsecond photoresist pattern.
 11. The method as set forth in claim 10,wherein said second photoresist pattern layer has a plurality ofpatterns on said recess portion of said metal layer.
 12. The method asset forth in claim 10, wherein a throughhole is formed said firstphotoresist pattern layer in on said plane portion of said metal plate.13. The method as set forth in claim 10, wherein said second metal layerforming step forms said second metal layer by using a plating process.14. A method for manufacturing a package, comprising: providing aphotoresist pattern layer having a plurality of patterns on a recessportion of a metal plate, so that a plurality of protrusions are formedon said recess portion of said metal plate; and etching a second metallayer and said recess portion of said metal plate by using a secondphotoresist pattern.
 15. A method for manufacturing a package includinga plate including a recess portion and a plane portion, comprising:forming a photoresist pattern layer for covering said plane portion ofsaid plate; and etching said plate by using said photoresist patternlayer as a mask, wherein said photoresist pattern layer has a pluralityof patterns on said recess portion of said plate, so that a plurality ofprotrusions are formed on said recess portion of said plate.